Within a data processing apparatus having a plurality of master logic units and slave logic units, it is known to provide interconnect logic for coupling the master logic units and the slave logic units to enable transactions to be performed. Each transaction consists of an address transfer from a master logic unit to a slave logic unit, and one or more data transfers between that master logic unit and that slave logic unit. For a write transaction these data transfers will pass from the master logic unit to the slave logic unit (in some implementations there will additionally be a write response transfer from the slave logic unit to the master logic unit), whilst for a read transaction these data transfers will pass from the slave logic unit to the master logic unit.
The interconnect logic will provide a plurality of connection paths for coupling the various master logic units and slave logic units. The way in which the various transfers are routed via those connection paths will be dependent on the bus protocol employed within the interconnect logic. One known type of bus protocol is the non-split transaction protocol, such as is employed within a data processing apparatus having an AHB bus designed in accordance with the AHB bus protocol developed by ARM Limited, Cambridge, United Kingdom. In accordance with such a non-split transaction protocol, there is a fixed timing relationship between the address transfer of a transaction and the subsequent one or more data transfers of that transaction. In particular, the data transfer starts in the cycle following that in which the address is transferred. Within such a design, it is known to provide an address arbiter to arbitrate between multiple address transfers seeking to use a particular connection path. Due to the fixed timing relationship between the address transfers and data transfers, then it will be appreciated that the data transfers of multiple transactions occur in the same order as the arbitrated address transfers.
As interconnect logic increases in complexity, due to the need to support the interconnection of a larger number of master and slave logic units, then another type of bus protocol has been developed known as a split transaction protocol. In accordance with such a split transaction protocol, the plurality of connection paths within the interconnect logic provide at least one address channel for carrying address transfers and at least one data channel for carrying data transfers. An example of such a split transaction protocol is the AXI (Advanced extensible Interface) protocol developed by ARM Limited, Cambridge, United Kingdom. The AXI protocol provides a number of channels over which information and data can be transferred, these channels comprising a read address channel for carrying address transfers of read transactions, a write address channel for carrying address transfers of write transactions, a write data channel for carrying data transfers of write transactions, a read data channel for carrying data transfers of read transactions, and a write response channel for returning transaction status information to the master logic unit at the end of a write transaction, such transaction status information indicating for example whether the transaction completed successfully, or whether an error occurred, etc. Use of such a split transaction protocol can increase the performance of a system compared with a similar system using a non-split transaction protocol.
Conventionally, when adopting such a split transaction protocol, data transfers over a data channel are prioritised according to the temporal ordering of the corresponding address transfers over the relevant address channel, such that data pertaining to earlier addresses (i.e. addresses transferred earlier over the address channel) are given priority over data pertaining to later addresses. This approach models closely the situation occurring in a non-split transaction protocol where the address and data are tightly coupled, and results in a balanced service to every master and slave logic unit coupled to the interconnect logic. However, such an approach does not make the most efficient use of the interconnect logic, and it is often the case that master devices will be stalled whilst waiting for the data transfers of particular transactions to take place.
An enhancement that may be used to allow some local re-ordering of transactions at a particular slave logic unit when using interconnect logic conforming to such a split transaction protocol is described in U.S. patent application Ser. No. 10/743,537 filed on 23 Dec. 2003, now U.S. Pat. No. 7,181.556, for which ARM Limited is the assignee. In accordance with the teaching of this application, each address transfer includes a source identifier identifying the source of the transaction. Preferably, each master logic unit has a plurality of possible source identifiers that can be associated with transactions that it issues. This has the advantage that, for example, transactions generated by different applications running on the same processor can be distinguished so that transaction sequences from each application can be independently ordered in cases where the processes themselves are independent of each other. A slave device can then perform some local reordering of pending transactions it has to service based on such source identifier information, such that, for example, the one or more data transfers associated with a transaction issued with a particular source identifier can be given priority over the one or more data transfers associated with an earlier pending transaction issued with a different, lower priority, source identifier.
However, whilst such an approach enables some local reordering at particular peripheral slave devices, it still suffers from the problem of not making the most efficient use of the interconnect logic, and accordingly can still give rise to situations where master logic units are stalled pending completion of the data transfers of particular transactions.
In the unconnected technical field of network-on-chip designs, it is known to allow particular nodes in the network to reorder read data packets based on a concept of priority.
It would be desirable to provide an improved technique for handling transactions within the interconnect logic of a data processing apparatus so as to make more efficient use of the resources of the interconnect logic in situations where a split transaction protocol is being used.